Design for Testability of an Asynchronous Adder

Modern technological processes for producing VLSI circuits have created an opportunity to exploit the advantages of asynchronous circuits. Compared to their synchronous counterparts, asynchronous circuits have the potential for lower power consumption, offer greater design flexibility, exhibit average rather than worst-case performance and have no problem with clock skew [Lav93, Hauck95]. Asynchronous circuits can be divided into three major groups depending on the delay model assumption chosen: delay-insensitive, speed-independent and bounded-delay circuits [Lav93, Birt95, Brzo95]. In delay-insensitive circuits, gate and wire delays are unconstrained but finite. Speed-independent circuits also operate correctly regardless of their gate delays, but signal transmissions along their wires are assumed to be instantaneous. All delays within bounded-delay asynchronous circuits are constrained. Data in asynchronous circuits can be represented using either dual-rail or single-rail data encoding techniques. In the dual-rail data representation each bit of data is encoded using two wires. In four-phase dual-rail encoding, a high logic level on the ‘one’ or ‘zero’ wire and a low logic level on the corresponding ‘zero’ or ‘one’ wire indicates the transmission of a one or a zero respectively. If both data wires are set to zero data is not valid. The state ‘11’ is illegal. In the single-rail encoding a bit of data is represented by the logic level on one wire.